soc-freedom-sifive

e300 and u500 devkits

created at June 22, 2019, 1:50 a.m.

Scala

8

8

5

GitHub
freedom

Source files for SiFive's Freedom platforms

created at Nov. 24, 2016, 12:15 a.m.

Scala

173

956

245

GitHub
sifive-blocks

Common RTL blocks used in SiFive's projects

created at Nov. 24, 2016, 12:16 a.m.

Scala

52

151

79

GitHub
fpga-shells

None

created at July 24, 2017, 9:17 p.m.

Scala

45

116

60

GitHub
soc-iofpga-sifive

An IOFPGA SoC

created at June 18, 2019, 12:10 a.m.

Scala

28

0

0

GitHub
block-pio-sifive

An example of on-boarding a PIO block in with duh and wake

created at June 17, 2019, 6:34 p.m.

Scala

13

10

14

GitHub
soc-testsocket-sifive

A simple SoC for testing IP blocks

created at June 17, 2019, 5:41 p.m.

Scala

29

11

4

GitHub
block-inclusivecache-sifive

None

created at June 22, 2019, 1 a.m.

Scala

10

49

36

GitHub
example-chisel-iotester-wake

None

created at July 16, 2019, 1:06 a.m.

Scala

3

1

1

GitHub
block-lpddr4_ctrl-samsung

debug only

created at Jan. 20, 2020, 3:54 p.m.

Scala

5

0

0

GitHub
chisel-circt

Library to compile Chisel circuits using LLVM/MLIR

created at Jan. 14, 2021, 4:29 p.m.

Scala

5

0

0

GitHub