chisel

Chisel: A Modern Hardware Design Language

created at April 27, 2015, 10:55 p.m.

Scala

149

3,712

571

GitHub
rocket-chip

Rocket Chip Generator

created at Sept. 12, 2014, 7:04 a.m.

Scala

196

3,012

1,067

GitHub
treadle

Chisel/Firrtl execution engine

created at Jan. 17, 2018, 7:34 p.m.

Scala

30

139

29

GitHub
cde

A Scala library for Context-Dependent Environments

created at Aug. 3, 2019, 12:21 a.m.

Scala

18

39

20

GitHub
rocket-chip-inclusive-cache

An RTL generator for a last-level shared inclusive TileLink cache controller

created at June 1, 2022, 6:25 p.m.

Scala

14

13

12

GitHub
rocket-chip-blocks

RTL blocks compatible with the Rocket Chip Generator

created at June 1, 2022, 4:59 p.m.

Scala

15

12

14

GitHub
t1

None

created at Sept. 18, 2022, 12:09 a.m.

Scala

9

79

12

GitHub
chisel-template

A template project for beginning new Chisel work

created at Feb. 23, 2016, 10:59 p.m.

Scala

50

519

169

GitHub
diplomacy

None

created at Aug. 26, 2021, 8:56 a.m.

Scala

23

16

7

GitHub
api-config-chipsalliance

A Scala library for Context-Dependent Evironments

created at Aug. 3, 2019, 12:21 a.m.

Scala

9

14

14

GitHub
chisel3

Chisel 3: A Modern Hardware Design Language

created at April 27, 2015, 10:55 p.m.

Scala

153

2,930

508

GitHub
firrtl

Flexible Intermediate Representation for RTL

created at Feb. 13, 2015, 11:04 p.m.

Scala

63

694

175

GitHub
rocket-chip-fpga-shells

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

created at June 1, 2022, 6:43 p.m.

Scala

14

14

16

GitHub
playground

chipyard in mill :P

created at Dec. 10, 2019, 6:08 p.m.

Scala

10

56

29

GitHub